Page Tables (see Fig. 4.12)

Figure 4.12: The internal operation of the MMU with 16 4-KB pages.

• Page table kept in main memory
• The Modified and Referenced bits keep track of the page usage. If the page in it has been modified, it must be written back to the disk. This bit s sometimes called the dirty bit.
• Page-table base register (PTBR) points to page table
• Page-table length register (PRLR) has size of page table
• In this scheme every data/instruction access needs 2 memory accesses: page table and data/instruction
• 2-memory access problem can be solved by special fast-lookup hardware cache using associative memory called translation look-aside buffer (TLB)
• Address space may be very large, e.g.:
  • 32-bit addresses 4GB
  • 64-bit addresses millions of TB
• May have big gaps (sparse), e.g.
  • stack grows down from high memory
  • dynamic allocation grows up from low memory
• Page table very large, big waste of memory