Direct Memory Access (DMA)

Figure 5.5: The Process to Perform DMA Transfer.

• Takes control of the bus from the CPU to transfer data to and from memory over the system bus
• Cycle stealing is used to transfer data on the system bus
• The instruction cycle is suspended so data can be transferred
• The CPU pauses one bus cycle, CPU Cache can hopefully avoid such pauses
• Reduced number of interrupts occur, No expensive context switches
• Cycle stealing causes the CPU to execute more slowly; Still more efficient than CPU doing transfer itself
• The CPU cache can hide some bus transactions
• Number of required busy cycles can be cut by
  • integrating the DMA and I/O functions
  • Path between DMA module and I/O module that does not include the system bus
• The Process to Perform DMA Transfer (see Fig. 5.5)
  1. device driver is told to transfer disk data to buffer at address X
  2. device driver tells disk controller to transfer C bytes from disk to buffer at address X
  3. disk controller initiates DMA transfer
  4. disk controller sends each byte to DMA controller
  5. DMA controller transfers bytes to buffer X, increasing memory address and decreasing C until C=0
  6. when C=0, DMA interrupts CPU to signal transfer completion