Bus Synchronization

• A bus can be classified as synchronous or asynchronous.
  • The time for any transaction over a synchronous bus is known in advance. In accepting and/or generating information over the bus, devices take the transaction time into account.
  • Asynchronous bus, on the other hand, depends on the availability of data and the readiness of devices to initiate bus transactions.
• In a single bus multiprocessor system, bus arbitration is required in order to resolve the bus contention that takes place when more than one processor competes to access the bus.
  • The bus arbitration logic decides, using a certain priority scheme, which processor will be granted access to the bus during a certain time interval (bus master).
    • Random priority,
    • simple rotating priority; after each arbitration cycle all priority levels are reduced one place, with the lowest priority processor taking the highest priority.
    • Equal priority; when two or more requests are made, there is equal chance of any one request being processed.
    • Least Recently Used (LRU) priority; the highest priority is given to the processor that has not used the bus for the longest time.
  • The process of passing bus mastership from one processor to another is called handshaking and requires the use of two control signals: bus request and bus grant.
    • the first indicates that a given processor is requesting mastership of the bus,
    • the second indicates that bus mastership is granted.
    • a third signal, called bus busy, is usually used to indicate whether or not the bus is currently being used.