Classification of Shared Memory Systems

Figure 4.2: Shared memory via two ports.

• The simplest shared memory system consists of one memory module (M) that can be accessed from two processors P1 and P2 (see Fig. 4.2).
  • Requests arrive at the memory module through its two ports. An arbitration unit within the memory module passes requests through to a memory controller.
  • If the memory module is not busy and a single request arrives, then the arbitration unit passes that request to the memory controller and the request is satisfied.
  • The module is placed in the busy state while a request is being serviced. If a new request arrives while the memory is busy servicing a previous request, the memory module sends a wait signal, through the memory controller, to the processor making the new request.
  • In response, the requesting processor may hold its request on the line until the memory becomes free or it may repeat its request some time later.
  • If the arbitration unit receives two requests, it selects one of them and passes it to the memory controller. Again, the denied request can be either held to be served next or it may be repeated some time later.